The present invention relates to an Electrostatic Discharge (ESD) protection device according to the preamble of the first claim.
The more and more extensive use of smart power technology in demanding environments, such as automotive applications, requires appropriate and specific Electro Static Discharge (ESD) protection devices. Integrated circuits (IC) used for such harsh applications require a high ESD robustness and latch-up free operation and they have to operate at high operating temperatures and voltages. FIG. 1 shows a current voltage curve of a typical prior art bipolar ESD device, having a breakdown voltage Vbd of about 65V, a trigger voltage Vt of about 95V and a holding voltage Vh of about 40V.
To provide an effective ESD protection for the whole integrated circuit, on-chip ESD protection circuits are added to the input/output pads (I/O) (1) and supply pads (7) of the IC (2) (cf. FIG. 2). The specifications of such on-chip ESD protection circuits such as triggering voltage and holding voltage are different for an Input/Output structure (I/O-port) and a power supply. In case of e.g. an I/O-port shown in FIG. 2a, a voltage peak Vp or discharge on the input bonding pad (1) transferred to the chip (2) must be limited in order to prevent damage of the input of subsequent devices and circuits (2). This requires an ESD device (3) that triggers and holds at a low voltage, avoiding a permanent overload of the circuit (2). The breakdown voltage Vbd and trigger voltage Vt such ESD device must be less than a specified maximum voltage Vmax. On the other hand a power supply line providing power from the supply pad (7) to the circuit (2), as shown in FIG. 2b, must maintain a high enough voltage, to prevent unwanted switching off of a circuit due a voltage drop on this supply line. This requires an ESD device (3) with a breakdown voltage Vbd and a holding voltage Vh that are above a minimal voltage Vmin to maintain a specified minimal supply voltage. Table 1 summarises typical requirements for an ESD structure used in I/O and power supply of an integrated circuit to be used in automotive applications. The corresponding ESD protections are nowadays designed for each application or circuit.
From WO-A-99/21229, a self-triggered bipolar device is known which is used as ESD protection device in smart power technology. WO-A-99/21229 describes a lateral bipolar device used as an electrostatic discharge device. The collector of this bipolar device consists of a highly doped region and a lowly doped region adjacent to the base region. The voltage applied to the collector electrode at which this bipolar device triggers, depends on the width of this lowly doped collector region. In other words, the width of this lowly doped collector region is a layout parameter which can be predetermined for selecting a desired trigger voltage of the bipolar device. The holding voltage of the bipolar device is however substantially independent from this parameter.
It is an aim of the present invention to provide an electrostatic discharge device of which the holding voltage can be predetermined.
For the purpose of clarity, the invention will be described in the following for an npn bipolar device. However, it should be apparent that the invention also relates to pnp bipolar devices.
The (npn) ESD protection device according to one aspect of the invention comprises a first highly p-doped region provided with a base contact, a first highly n-doped region provided with a collector contact and, in between, a second highly n-doped region provided with an emitter contact. The first highly doped p-doped region and the second highly n-doped region are applied or formed in a weakly p-doped region. This weakly p-doped region has a lateral overlap which extends towards the first highly n-doped region, the lateral overlap has a predetermined width xe2x80x9cdxe2x80x9d. The first highly n-doped region is applied in a weakly n-doped region. This weakly n-doped region and the weakly p-doped region are applied in a more weakly n-doped region. A highly n-doped buried layer (BLN) is located underneath the more weakly n-doped region and extends below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.
The first highly p-doped region has a doping concentration above that of the weakly p-doped region. The first highly n-doped region has a doping concentration above that of the weakly n-doped region, which in turn has a doping concentration above that of the weakly n-doped region. The highly n-doped buried layer (BLN) has a doping concentration above that of the weakly n-doped region. Because of its structure, the ESD device is provided for enabling a lateral current component from the first highly n-doped region in the direction of the second highly n-doped region and a vertical current component from the BLN in the direction of the second highly n-doped region.
In order to control the holding voltage of the ESD-device according to the invention, the layout parameter xe2x80x9cdxe2x80x9d is varied. It has been found that by varying the xe2x80x9cdxe2x80x9d parameter, it can be determined how electrical current will flow through the device in holding state, i.e. after the breakthrough voltage is reached and the device snaps back to the holding voltage. At smaller values of xe2x80x9cdxe2x80x9d, the current will flow more laterally, i.e. more near the surface of the device, than at larger values of xe2x80x9cdxe2x80x9d, at which the current will flow more vertically. In other words, for smaller values of xe2x80x9cdxe2x80x9d the lateral current component is favoured, whereas for larger values of xe2x80x9cdxe2x80x9d the vertical current component is favoured. Because of this possible selection between the vertical and the lateral current components, multiplied by the collector resistance of the device in the conductive state, the xe2x80x9cdxe2x80x9d parameter enables a selection in a range of obtainable holding voltages for the ESD device of the invention in the conductive state.
In the ESD device of the invention, the more weakly n-doped region separates the weakly n-doped region from the BLN. This means that a sinker region is omitted in the device of the invention. Such a sinker region is used in the prior art to connect the weakly n-doped region with the BLN and forms a reduction in the collector resistance of the device. However, this reduction in the collector resistance doesn""t provide an adequate solution in the device of the invention, as this leads to a predominance of the vertical current component. The xe2x80x9cdxe2x80x9d parameter would have to be chosen so small in order to make the lateral current component dominant, that there would be substantially no lateral overlap of the weakly p-doped region left. The width of the overlap would have to be reduced to a physically unobtainable size. So if a sinker region were present, it would become substantially impossible to select a ration for the lateral and the vertical current components and as such substantially impossible to obtain a desired holding voltage of the device by choosing a value for xe2x80x9cdxe2x80x9d.
Furthermore, the implementation of a sinker region in an ESD device requires a full BiCMOS process. Omitting the sinker region has the economic advantage that the device of the invention can be produced in a simplified or reduced BiCMOS process, which makes it possible to reduce the number of patterning and implementation steps.
An advantage of the present invention is that it offers an ESD structure with which a desired holding voltage can be easily achieved by adapting the layout. As this can be achieved by changing only one layout parameter, this offers an easy, flexible and cost-effective solution.
Because of the above-described structure of the ESD device according to the invention, the device can be seen as comprising a lateral transistor and a vertical transistor. The lateral transistor enables the lateral current component and is formed by the sequence of the second highly n-doped region, the weakly p-doped region, the weakly n-doped region and the first highly n-doped region. The vertical transistor enables the vertical current component and is formed is formed by the sequence of the second highly n-doped region, the weakly p-doped region, the more weakly n-doped region and the highly n-doped buried layer. By varying the width xe2x80x9cdxe2x80x9d of the lateral overlap of the weakly p-doped region according to the invention, it can be determined which of these two transistors xe2x80x9csnaps backxe2x80x9d first, i.e. which of these two transistors becomes active at the triggering voltage of the device and will, as a result, determine the holding voltage of the device in use. Preferably, xe2x80x9cdxe2x80x9d is chosen such that the holding voltage of the device is determined by either the lateral or the vertical transistor. Choosing xe2x80x9cdxe2x80x9d in such a way that the holding voltage is only determined by either the lateral or the vertical transistor has the advantage that the stability of the holding voltage can be enhanced, i.e. that the current dependency of the holding voltage can be reduced.
For lower values of xe2x80x9cdxe2x80x9d, the holding voltage is determined by the lateral transistor, whereas for higher values of xe2x80x9cdxe2x80x9d, the holding voltage is determined by the vertical transistor. For intermediate values of xe2x80x9cdxe2x80x9d, the lateral and vertical transistors are in competition, which leads to a holding voltage having an intermediate value.
Preferably, the more weakly n-doped region separates the weakly p-doped region and the weakly n-doped region by a first predetermined distance xe2x80x9ctxe2x80x9d. This distance xe2x80x9ctxe2x80x9d can be chosen in function of the trigger voltage of the device in use.
In a preferred embodiment of the ESD device according to the invention, a second highly p-doped region is provided in the lateral overlap of the weakly p-doped region. This second highly p-doped region changes the carrier density in the lateral overlap and hence the gain of the lateral device. Providing the second highly p-doped region in the lateral overlap has the same effect as choosing a larger value for the width xe2x80x9cdxe2x80x9d of the lateral overlap. In this way, providing the second highly p-doped region allows a reduction of the width xe2x80x9cdxe2x80x9d of the lateral overlap in comparison with a lateral overlap without such second highly p-doped region. This has the advantage that the size of the ESD device of the invention can be reduced.
In another preferred embodiment of the ESD device according to the invention, the buried layer is laterally separated from the second highly n-doped region by a second predetermined distance xe2x80x9cbxe2x80x9d. A lateral separation may also be applied on the other side of the buried layer, namely by laterally separating the buried layer from the first highly n-doped region by a third predetermined distance xe2x80x9ccxe2x80x9d. The lateral separations xe2x80x9cbxe2x80x9d and xe2x80x9ccxe2x80x9d may also be combined. Laterally separating the buried layer on one or both sides involves an increase in the collector resistance of the vertical bipolar and as such forms an alternative way of controlling the holding voltage of the device. In other words, the distances xe2x80x9cbxe2x80x9d and xe2x80x9ccxe2x80x9d form further parameters for tuning the holding voltage of the device in use.
In the ESD device of the invention, the weakly p-doped region preferably separates the first highly p-doped region from the second highly n-doped region. The first highly p-doped region and the second highly n-doped region may however also contact each other.
In another embodiment of the ESD device of the invention, the weakly p-doped region contacts the weakly n-doped region, i.e. the xe2x80x9ctxe2x80x9d-parameter is chosen zero. As a result, a predetermined selection of the trigger voltage is not possible in this embodiment. It can however be advantageous when such a selection is unimportant, as this embodiment has a simpler structure.
The invention also relates to devices comprising first and second ESD devices according to one of the above-described embodiments, the width xe2x80x9cdxe2x80x9d of the overlap of the first ESD device being different from that of the second ESD device. In this way a device is provided which is suitable for sustaining two different holding voltages, one being determined by the first ESD device and the other by the second ESD device.